Keynote Speakers

ISSE 2024 Keynote Speakers

Keynote speaker: Jakub Altman
Job position: Process Engineer
Company: Continental Brandýs nad Labem

Title of the presentation:
AI in production – Magic AOI

Short CV:

  • Graduated high school of civil aviation.
  • More than 5 years of experience at Ruzyne civil airport ended up in the position of supervisor.
  • 3 years of experience in automotive in the quality department
  • More than 5 years of experience as a process engineer in SMT area for Continental company – specialization in automatic optical inspection systems.


  • SMT pool introduction
    • Structure, lines, production
  • AOI machine description
  • Magic AOI description
    • function, principles, roadmap
  • Project details
    • components, automated evaluation process
  • KPI (key performance indicators)
    • Workload, escapes

Keynote Speaker / Distinguished Lecturer: John H Lau.
Job position: Senior Special Project Assistant
Company: Unimicron

Title of the presentation:
Chiplet Design and Heterogeneous Integration Packaging

Short CV:

John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 530 peer-reviewed papers (385 are the principal investigator), 52 issued and pending US patents (31 are the principal inventor), and 23 textbooks (all are the first author). John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.


In this lecture, the following topics will be covered: (1) System-on-Chip (SoC); (2) Why Chiplet Design; (3) Chiplet Design and Heterogeneous Integration Packaging (a) Chip Partition and Chip Split, (b) Chip partition and Heterogeneous Integration, (c) Chip split and Heterogeneous Integration, and (d) Advantages and Disadvantages; (4) Lateral Communication between Chiplets (e.g., Bridges) (a) Bridge Embedded in Build-up Package Substrate, (b) Bridge Embedded in Fan-Out EMC with RDLs, (c) UCIe, and (d) Hybrid Bonding Bridge; (5) Chiplet Design and Heterogeneous Integration Packaging (a) Multiple System and Heterogeneous Integration with Package Substrate (2D IC Integration), (b) Multiple System and Heterogeneous Integration with Thin Film layer on the Package Substrate (2.1D IC Integration), (c) Multiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration), (d) Multiple System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC Integration) for artificial intelligence applications, and (e) Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration); (6) Summary; (7) Trends in Chiplet Design and Heterogeneous Integration Packaging.

Keynote speaker: Dr Napetschnig Evelyn
Job position: Lead Principal Engineer
Company: Infineon Technology Austria AG

Title of the presentation:
10 Golden Rules of Chip- Package- Board Interactions

Short CV:

02/2020 – current: lecturer @ Montanuniversität Leoben

01/2008 – current: Engineer @ Infineon Technologies Austria AG

Since 04/2021: Lead Principal Engineer

10/1995 – 11/2008: Master and PhD studies in technical physics at the Vienna University of Technology


As they strive to reach even better technology solutions in even faster time the semiconductor industry engineers of today tend to forget about basic principles. The ten golden rules aim to support the engineers to find the best solution by questioning the right way. As the rules are very basic every engineer in the semiconductor industry can apply them. Most experienced technical experts have come together and formulated the rules, thus, best results are granted as the worst failure paths are included enabling a faster time to market while implementing highly reliable stable processes in the end. On the first sight some of the rules are very basic technical common sense, but too often the basic principles are overseen during project planning and will lead to issues, delays and even fail and cancelation of the projects. This list of ten golden rules can be print out on one sheet, placed on every table of a semiconductor engineer and can act as a reminder to respect the most basic principles of material science, mechanics, thermodynamics and electronics while keeping an eye on the productivity. Omitting the 10 golden rules is helping to decrease the complexity of the available process and thus allow approaching the highest quality requirements that are given by the current market. 

Keynote speaker: Dr.-Ing. Franz Röhrl
Job position: Head of PCB Technology
Company: Rohde & Schwarz GmbH & Co. KG | Plant Teisnach

Title of the presentation:
Technological status quo for high-end RF printed circuit Board development at Rohde & Schwarz

Short CV:

received the M.Sc. degree in electrical engineering and information technology from the Technical University of Munich (TUM), Munich, Germany, in 2013, and the Dr. Ing. degree from Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany, in 2020. Since 2014, he has been holding a Lectureship position with Deggendorf Institute of Technology, Deggendorf, Germany, with a focus on RF circuitry. In parallel, since 2023, he has also been the head of research and development PCB technology with Rohde & Schwarz GmbH & Company KG, Teisnach, Germany.


Discover the technological way from a conventional to a RF PCB for millimeter wave applications.

Within the talk you will learn about the technological needs and the advantages to use PCBs for applications in this frequency range.

The session will close with an outlook on technical PCB based solutions for next generation microwave applications.

Keynote speaker: Prof. Dr. Nihal Sinnadurai
Job position: CTO
Company: ATTAC

Title of the presentation:
Contrasting Reliable Systems – Automotives and Mobiles

Short CV:

Honours Graduate in Physics, London, Post-Grad, Southampton, England

Life Fellow IEEE, Life Fellow Institute of Physics, Chartered Engineer

Lifetime Achievement from IEEE Reliability Society

Chair IEEE Region 8 ‘Action for Industry

Former Corporate Director and Vice President Oclaro (Photonics)

Former Chief of BT Intelligent Networks developments


The Environments and Required Lifetimes are different for automotive and mobile devices. But the fundamentals are similar – evidence must support reliability decisions.

The environments for electronics (and photonics). within conventional automotives can be a harsh, and the external environments may also be harsh. Nevertheless automotives are required to achieve reliable (and repairable) lifetimes of 15 years. By contrast, mobile device environments and lifetimes are akin to consumer products – the smart-phone replacement cycle on average is now within two years, which is well inside any reasonable lifetime of consumer electronics.

The move to hybrid and electric vehicles is changing the automotive industry. EVs on the roads are expected to grow to 35 million by 2030. The complexion of under-the-hood environment then changes dramatically from a hot environment to nearer the external ambient.

Growth in functionality is normal – with consequent demands  on the supply of ICs and applications software. Reliability assurance and fault tolerance are essential where lives may be at risk, such as in automotives. While we may imagine that mobiles are not critical to life, there are enhanced difficulties in dealing with robustness and security issues when the end-goal is to deploy security-enhanced smart phones into military combat settings, and low earth orbit satellites (LEOS).

Reliability assurance processes delivering evidence are in place whatever the application.

Keynote speaker: Ing. Vladimír Sítko
Job position: Founder, Mentor, Co-owner
Company: PBT Works s.r.o.

Title of the presentation:
Component packages and their influence on the climatic reliability of assemblies

Short CV:

Vladimir Sitko is a founder and mentor of PBT Works s.r.o, a recognized manufacturer of electronic assembly cleaning systems.

After finishing his studies at Technical University (nearly 50 years ago), he worked as a designer of measuring devices for silicon analysis and machines for active component production.

In 90-ties, he started a company for process integration and consulting in SMT assembly. At the same time, that company has designed the first cleaning machines for PCBA. Systems for Cleaning microelectronics have become his primary focus until now. More than 30 years of experience gave him much information on increasing the reliability of electronics by cleaning. He participates in several research tasks for cleaning technology and electrochemical corrosion. He owns several patents for details of cleaning machines and test tools.


The safe level of contamination for a specific electronic assembly (PCBA) depends on the sensitivity of the electronic circuitry, components used to build it and environment that affects the assembly.

Miniaturized components, especially bottom terminated (BTC), such as QFNs, µBGAs, and LGAs, are soldered to the bottom terminations. The common feature of such mounted components is a shallow standoff gap. During the soldering process, flux residues accumulate under components, and block flux outgassing. Incomplete flux outgassing leaves some volatile compounds in the critical space. That increases the ion mobility and can cause electrochemical migration. Also, in extreme temperatures and vacuum, the residual volatile compounds can disturb the cleanliness of surrounding places and cause corrosion or insulative failures on the assembly by re-deposition of organics.

We picked some mechanical details, which are often underestimated during the package design. Respecting simple fluidic and thermodynamic rules by design might help save time and money. If cleaning is a part of the process, obstacles caused by design often cause challenging situations: too long exposure of components by chemistry, and compromised results in the final cleanliness.

To get more detailed information on behaving BTC components during soldering and cleaning, we developped a novel tool – glass test boards, which enables easy observation of the soldering and cleaning result, easy measuring of any unwanted tilting of components during soldering and also testing of surface insulation resistance after process optimization.

We believe the modeling by Glass Test Boards is effective and can bring another level of knowledge on behaving complex packages during the assembly. Also, it can be utilised in optimising and qualification of cleaning process, coating, underfill and other operations.

Keynote speaker: Ing. Václav Wirth, Ph.D.
Job position: Technologist – project leader
Company: Rohde & Schwarz závod Vimperk, s.r.o.

Title of the presentation:
Soldering defects and their arduous solution in PCB assembly at Rohde & Schwarz

Short CV:

Václav Wirth graduated in Electrical Engineering and Informatics at the University of West Bohemia in Pilsen in 2017 (Ph.D.). The topic of the final thesis was “The Influence of Intermetallic Compounds on the Quality of Lead-Free Solder Joints”. He was a teaching and research assistant during his doctoral studies at the Department of Technologies and Measurement. Since 2015 he has been working for Rohde & Schwarz in Vimperk. He is gaining experience in the technological team for printed circuit board assembly with a specific emphasis on the interconnection of electronic components.


The session describes relatively common defects caused by the reflow soldering process. Solutions can be theoretically very easy, but in practice the solution is often unusable for production. Therefore, specific defects examples and general recommendations for corrections will be shown. On the contrary the implemented solution to the defect will be detailed to improve the PCB assembly process and product quality.